Bamboo is already shaking his head before Schnapps finishes the intro.
🐼 Bamboo: Sixty million dollars to replace chip designers with AI. Let me tell you what happens when you skip the physics. In 2023, Synopsys shipped DSO.ai and promised the same thing — automated place-and-route, shorter tapeout cycles. Two years later, every major foundry still has hundreds of human engineers hand-tuning timing closure. You know why? Because silicon doesn't forgive approximations.
🦁 Maximus: You're comparing a routing optimizer to what Cognichip is actually building. Their model is physics-inspired — it's not skipping the physics, it's encoding it. Intel's CEO joined their board. Lip-Bu Tan doesn't do vanity appointments. If this works at even half the claimed 75% cost reduction, every fabless company on earth rewrites their R&D budget overnight.
🦝 Schnapps: Let's put a number on "if this works." They say 30+ semiconductor partners. That's not a pilot — that's a pipeline. 💰
🐼 Bamboo: Thirty partners running proofs-of-concept is not thirty partners in production. I've watched this movie before. The demo looks magical — AI generates a floorplan in hours instead of weeks. Then you hit DRC violations at 3-nanometer, thermal hotspots the model never trained on, yield issues that only show up at volume. Cognichip's pitch deck says 50% faster timelines. The real question is: 50% faster to what? To first silicon? Or to production-grade silicon that actually ships in a phone?
🦁 Maximus: You're protecting the old workflow. I run engineering orgs. I know what chip design costs — $500 million to tape out a cutting-edge SoC, 18-month cycles, teams of 300. If Cognichip cuts that to $125 million and nine months, I don't care if version one has rough edges. I'll iterate. The economics alone justify the bet. And frankly, the talent bottleneck forces it — there aren't enough senior physical design engineers on earth to meet demand.
🐼 Bamboo: The talent bottleneck is exactly why this is dangerous. You need those senior engineers to validate what the AI produces. If you fire them to capture that 75% cost saving, who checks the output? Who catches the analog noise coupling the model has never seen? You're not replacing expertise — you're hiding your dependency on it behind a dashboard.
🦝 Schnapps: So Bamboo says the humans are the safety net, and Maximus says the humans are the bottleneck. That's the whole tension right there. 🔍
🦁 Maximus: It's not either-or. It's leverage. Ten engineers plus Cognichip's platform do what 100 did before. But Bamboo's acting like AI-generated chip designs ship without verification. Nobody's skipping sign-off. You still simulate, you still run DRC, you still validate timing. The AI compresses the exploration phase — it doesn't delete the verification phase.
🐼 Bamboo: Then your 50% timeline claim evaporates. Verification is 60% of the cycle. If you only compress exploration, you save maybe 20%. That's nice. That's not a revolution. That's a feature inside Cadence.
🦝 Schnapps: Last week Google's TurboQuant paper crashed memory chip stocks by making existing hardware more efficient. Now Cognichip wants to make designing new hardware cheaper. One shrinks demand, the other shrinks supply cost. If both land, the semiconductor industry's margin structure looks completely different by 2028.
🐼 Bamboo: If both land. That's carrying a lot of weight.
🦁 Maximus: Sixty million says somebody thinks it can.
